In Verilog, if you want to create sequential logic use a clocked always block with nonblocking assignments. However, I would say that your code is combinational because it is not synchronized with clk signal and the ouput is changed according to a or b inputs and the output does not depend on previous state (such as q <= ~q). Also a rule of thumb is to use only blocking assignments in an block (e.g OUT = A & B).Ĭoncerning your verilog code, there is a CLK signal in your sensitivity list and non-blocking assignments are used (which are used only in sequential logic circuits). Which signals should trigger the elements inside the block to be updated. The star (*) represents the sensitivity list specifies 1.10(a) shows that an inferred latch DIGITAL LOGIC REVIEW WITH VERILOG. Regarding verilog code, one way to find out the combinational part from your module is to see the always block and its sensitivity (*) block is used to describe combinational logic and logic gates. does not imply that this net is driven by a register or sequential logic. In case that one of those conditions are not met, your circuit is sequential. Also a combinational circuit is time independent. So, I suppose I need to look deeper into my code and figure out why I am getting the timing errors. For example, an SR-Latch has a set and a reset input and if either of them are active then the output can change. So, it seems that my implementation wasn't necessarily wrong, but perhaps leaves a little too much to the imagination, unnecessarily (especially for people like me who are new to Verilog). A latch can change its output in response to something other than a clock. You can find out if a circuit is combinational if the circuit does not depend on previous states. A 'latch' is different from a 'Flip-Flop' in that a FF only changes its output in response to a clock edge.
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